Equation solving

Referring to the n-MOS chain in figure 3.3, we can write at the output node $N$:

$$Q_n^N = -Q_C^N=-C^N V_{d_n}^N$$ (4.8)

because, neglecting the contribution of the p-MOS chain above (if it exists), $Q_I^{N}=0$.

At the node $N-1$ we can write:

$$Q_n^{N-1} = Q_I^{N} - Q_I^{N-1}-Q_C^{N-1}\; ,$$

and combining with eq. (3.7) (page )

$$Q_n^{N-1}=-C^N V_{d_n}^N- Q_I^{N-1}-Q_C^{N-1}\; ,$$

and so on:

$$Q_n^{N-2}=-C^N V_{d_n}^N- C^N V_{d_n}^{N-1}-Q_I^{N-1}-Q_C^{N-2}\;.$$

More generally:

$$\begin{split}Q_n^{i} & = -\sum_{k=i+1}^{N} C^k V_{d_n}^k-Q_I^... ...} \\ & = -\sum_{k=i}^{N} C^k V_{d_n}^k-Q_I^{i} = 0 \end{split}$$

Proceeding till the first transistor, we obtain:

$$Q_n^{1}=-\sum_{k=1}^{N} C^k V_{d_n}^k-Q_I^{1}= 0\; ,$$ (4.9)

the same applies for p-MOSFETs.

In order to solve non-linear equation (3.8) one must substitute the definition of the current to calculate the charge $Q$, as in equations (3.6a), (3.6b) (page ), moreover one must substitute both the current calculated in the saturation region and the one calculated in the linear region, extending the integrals of the aforementioned equations to the proper extremes.

Finally we must distinguish among several different cases, depending on the instant of time on which the transistor switch from the saturation region to the linear region. For example, the first transistor can switches between the two regions when the rising of the input has already finished, or on the contrary can switches when the input is still rising.
All the possible cases are:

$$\begin{split}t_0^1 \leqslant t_s^1 \leqslant \tau_i^1 \leqsla... ...leqslant& t_0^1 \leqslant \tau_o^1\leqslant\tau_i^1 \end{split}$$ (4.10)

Evaluating all the possible cases, the equation (3.8) becomes a non-linear equation of the variables $t_s^1,\, t_0^1,\, \tau_o^1,\,\tau_i^1$, with $t_s^1,\, t_0^1,\, \tau_o^1$ as unknowns.
A further step must be done, with the purpose of eliminating all the variables but one. The real unknown is the time $\tau_o^1$, while all the other unknowns can be expressed in function of $\tau_o^1$: in particular, the times $t_s^1$ and $t_0^1$ can be calculated together, with the equation $V_{DS} = V_{GS}-V_{T}$and with the equation that states the charge conservation at node $1$ between the time 0 and the time $t_0^1$, similar to the equation (3.5) (page ), including the bootstrap effect due to capacitive coupling between the gate and the drain of the first transistor.
Both these equations are functions of $t_s^1,\, t_0^1,\, \tau_o^1,\,\tau_i^1$. By this way one has three equations with three unknowns, and by means of some approximated methods⁵it is possible to evaluate the three unknowns.

This solution scheme ought to be repeated for all the seven cases shown in equation (3.9). Each case gives as a solution a triple $t_s^1,\, t_0^1,\, \tau_o^1$ that is compatible with one and only one of the conditions expressed by these cases. Thus, only one working condition is really selected, as it can be expected.

Indeed all the previous solving scheme is true only if the equation (3.6c) (page ) apply, i.e. only if the capacitance at the node $i$ is not a function of the voltage at the same node. But the capacitance actually is function of the voltage in this manner:

$$C^i=C_j^i\left(1+\frac{V^i}{\Phi_b}\right)^{-m_j}+ C_p^i\left(1+\frac{V^i}{\Phi_b}\right)^{-m_p}$$ (4.11)

where $C_j$ and $C_p$ are, respectively, function of area and function of perimeter of a junction, because the capacitance at the node $i$ is due to the parasitics capacitances of the transistors connected to this node.

If the capacitance at each node are functions of the voltage at the node itself, then one equation is no more sufficient: one must write equations like the equation (3.8) (page ), one for each node, and the solve them with standard solving algorithm for non-linear equations. The only difference among the equations applied at the nodes above the first and the first node equation is that not all of the cases of equation (3.9) are possible: in particular these conditions apply only when the transistor can pass from the saturation region to the linear region, and moreover, only when the input rising time $\tau_i^1$ can assume whichever value. The passage from saturation to linearity can be made only by the first and the last transistors of the chain, as they are the only that can saturate⁶. But in the last transistor, the time $\tau_i^N$ is governed by $\tau_i^N=\tau_o^{N-1}$, giving thus only two possible cases:

$$t_0^N \leqslant t_s^N \leqslant\tau_i^N\leqslant\tau_o^N \qquad t_0\leqslant\tau_i^N\leqslant t_s^N \leqslant \tau_o^N$$

In order to make the algorithm convergent, two other fictitious cases must be included:

$$t_0^N \leqslant t_s^N ,\, \tau_o^N\leqslant\tau_i^N$$

$$t_0\leqslant t_s^N ,\,\tau_o^N\leqslant \tau_i^N$$

These conditions can never verify in a real circuit, since they imply that the voltages at the source node and at the drain node of the last transistor crosses, making the transistor current flowing in an inverse direction (see figure 3.6 for a visual explanation of the terms $\tau_i$ and $\tau_o$ and why they relative voltage waveforms cannot cross). Their inclusion help finding the real circuit conditions when solving the equation (3.8) for each of these four cases: the solution of one the fictitious cases gives only unknowns compatible with one of the real cases.

All the other transistors, that can not saturate during the switching from off to on, have only one possible working condition, again that the voltages at source and drain nodes do not cross:

$$\tau_i^j \leqslant \tau_o^j \quad \mathstrut{j=2,\dots N-1}$$

Solving all the equations, one for each node, the unknowns $\tau_o^j$ can be evaluated, giving thus an estimate of the voltage waveform at each node of the chain. The rising/falling time of the last node of the chain gives also the delay of the chain itself.